PIC16C58B-04/SS【PDF 78/194 页】IC MCU OTP 2KX12 20SSOP

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Sheet目录3889

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PIC18F2450/4450

2006 Microchip Technology Inc.

Advance Information

DS39760A-page 167

15.2.5

BREAK CHARACTER SEQUENCE

The EUSART module has the capability of sending the

special Break character sequences that are required by

the LIN bus standard. The Break character transmit

consists of a Start bit, followed by twelve ‘0’ bits and a

Stop bit. The Frame Break character is sent whenever

the

SENDB

and

TXEN

bits

(TXSTA<3>

and

TXSTA<5>) are set while the Transmit Shift Register is

loaded with data. Note that the value of data written to

TXREG will be ignored and all ‘0’s will be transmitted.

The SENDB bit is automatically reset by hardware after

the corresponding Stop bit is sent. This allows the user

to preload the transmit FIFO with the next transmit byte

following the Break character (typically, the Sync

character in the LIN specification).

Note that the data value written to the TXREG for the

Break character is ignored. The write simply serves the

purpose of initiating the proper sequence.

The TRMT bit indicates when the transmit operation is

active or Idle, just as it does during normal transmission.

See Figure 15-10 for the timing of the Break character

sequence.

15.2.5.1

Break and Sync Transmit Sequence

The following sequence will send a message frame

header made up of a Break, followed by an Auto-Baud

Sync byte. This sequence is typical of a LIN bus master.

Configure the EUSART for the desired mode.

Set the TXEN and SENDB bits to set up the

Break character.

Load the TXREG with a dummy character to

initiate transmission (the value is ignored).

Write ‘55h’ to TXREG to load the Sync character

into the transmit FIFO buffer.

After the Break has been sent, the SENDB bit is

reset by hardware. The Sync character now

transmits in the preconfigured mode.

When the TXREG becomes empty, as indicated by the

TXIF, the next data byte can be written to TXREG.

15.2.6

RECEIVING A BREAK CHARACTER

The Enhanced USART module can receive a Break

character in two ways.

The first method forces configuration of the baud rate

at a frequency of 9/13 the typical speed. This allows for

the Stop bit transition to be at the correct sampling

location (13 bits for Break versus Start bit and eight

data bits for typical data).

The second method uses the auto-wake-up feature

described in Section 15.2.4 “Auto-Wake-up on Sync

Break Character”. By enabling this feature, the

EUSART will sample the next two transitions on RX/DT,

cause an RCIF interrupt and receive the next data byte

followed by another interrupt.

Note that following a Break character, the user will

typically want to enable the Auto-Baud Rate Detect

feature. For both methods, the user can set the ABD bit

once the TXIF interrupt is observed.

FIGURE 15-10:

SEND BREAK CHARACTER SEQUENCE

Write to TXREG

BRG Output

(Shift Clock)

Start bit

bit 0

bit 1

bit 11

Stop bit

Break

TXIF bit

(Transmit Buffer

Reg. Empty Flag)

TX (pin)

TRMT bit

(Transmit Shift

Reg. Empty Flag)

SENDB

(Transmit Shift

Reg. Empty Flag)

SENDB sampled here

Auto-Cleared

Dummy Write

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